Vivado Build Flow — Brief ☧
*"According to the grace of God which is given unto me, as a wise
masterbuilder, I have laid the foundation, and another buildeth
thereon. But let every man take heed how he buildeth thereupon."*
— 1 Corinthians 3:10
Deep version → | Next: Our Architecture → | Back: Resources →
Q: You have written your hardware description in SystemVerilog.
But an FPGA does not understand SystemVerilog — it needs a binary
configuration file that tells each LUT and flip-flop exactly what to
do. How do you get from source code to a working chip?
A: Through the Vivado build flow — a multi-hour compilation
pipeline that transforms your human-readable design into a bitstream
the FPGA can load. Paul warns that "the fire shall try every man's
work of what sort it is" (1 Corinthians 3:13). Vivado is that fire:
it reveals every timing violation, every resource conflict, every
routing congestion you missed in your head.
Q: What are the actual stages? Walk me through it like I have
never seen it before.
A: Think of building a stone cathedral. There are distinct phases,
and you cannot skip ahead:
Source Code (SystemVerilog) | v Synthesis ---- "Quarry the stones" | Converts HDL into a netlist of FPGA primitives | (LUTs, flip-flops, BRAMs). ~30-60 minutes. v Placement ---- "Lay each stone in its place" | Assigns every primitive to a physical location | on the chip. ~60-90 minutes. v Routing ------ "Mortar the stones together" | Connects primitives with actual wires. | This is where timing closure is checked. | ~120-180 minutes. v Bitstream ---- "The finished cathedral" | Produces the binary configuration file. v AFI ---------- "Consecrate the cathedral" Registers the bitstream with AWS so it can be loaded onto an F2 instance.Q: That is a lot of time. What happens if routing fails but
synthesis was fine?
A: You do not start over. Vivado saves **Design Checkpoints
(.dcp)** at each stage — like a master builder who photographs the
foundation before building walls. If routing fails, you load the
post-synthesis checkpoint and try different routing strategies
(called "directives") without repeating the synthesis hour. This is
conceptually similar to how a version-control system lets you roll
back to a known-good state.
Q: How long does our full build take?
A: 3 to 5 hours on a c7i.4xlarge (32 GB RAM) for a full
V9.A/V9.D build. The build produces timing reports showing
WNS and TNS, resource utilization
summaries (see Resources), and a log of
every warning and error. Reading these reports is as important as
writing the SystemVerilog itself — the build output is the feedback
loop that guides your next design iteration.
Build Stage Summary
Here is the full pipeline at a glance. If you have experience with
software compilation, the rightmost column will help you map the
concepts to familiar territory.
| Stage | Time | Output | Software analogy |
|---|---|---|---|
| Synthesis | 30-60 min | Netlist (.dcp) | Compiling source to object files |
| Placement | 60-90 min | Placed design (.dcp) | Linking object files into a binary |
| Routing | 120-180 min | Routed design (.dcp) | Optimization pass + final link |
| Bitstream | ~10 min | .bit file | Packaging the executable |
| AFI | ~30 min | Amazon FPGA Image | Deploying to production |
Notice that routing alone takes 2-3 hours -- this is where the tool does
the hardest work, finding physical wire paths through a chip with over a
million logic elements. It is also where timing violations are discovered.
If routing fails, you do not need to repeat synthesis (the "compilation"
step) -- you can reload the placement checkpoint and try different routing
strategies, saving roughly 90 minutes per iteration. This checkpoint-based
workflow is essential when you are iterating on timing closure.
Soli Deo Gloria