Registers and Clocks — Brief ☧

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Q: In the Temple, the priests performed duties at fixed hours —

the morning sacrifice, the evening sacrifice. Everything was

synchronized to the rhythm of the day. What synchronizes an FPGA?

A: The clock. Think about a metronome ticking for a group of

musicians — everyone plays their note at the tick, and between ticks

they prepare the next note. An FPGA clock works the same way: it is a

periodic signal — rising, falling, rising, falling — like the heartbeat

of the Temple. On every rising edge (each "tick"), every flip-flop in

the design captures its input simultaneously.

Q: So what happens between the ticks?

A: That is when the actual computation runs. The LUTs evaluate

their boolean functions, signals ripple through wires, and

the result settles at the input of the next flip-flop — all before the

next tick arrives. It is like a relay race: between handoff points

(clock edges), the runner sprints. At the handoff point, the baton

(data) is passed cleanly.

Q: So the whole design is just "compute, capture, compute, capture"

repeating?

A: Exactly. This is the fundamental rhythm of all synchronous

digital hardware:
──┐  ┌──┐  ┌──┐  ┌──
  └──┘  └──┘  └──┘
  ^     ^     ^     ^
  |     |     |     |
  capture compute capture compute
At 250 MHz, one full cycle takes 4 nanoseconds — that is four

billionths of a second. All your combinational logic must finish its

work within that tiny window. If any path is too slow, data is not

ready when the clock ticks, and the flip-flop captures garbage. (We

will see how to measure this in Timing Closure.)

Two Kinds of Logic

With the clock rhythm in mind, we can now classify all digital logic into

two categories. Understanding this distinction is essential for everything

that follows in this module.

Type	Depends on	Contains	Example
Combinational	Current inputs only	LUTs, wires, muxes	`a AND b`
Sequential	Current inputs + stored state	Flip-flops	Counter, FSM

Combinational logic is like a transparent pipe: the output reflects the

current inputs with no memory of the past. If you feed in the same inputs,

you always get the same output. Our domain intersection (AND) is a

combinational operation -- it computes instantly based on the two input

domains with no need to remember anything.

Sequential logic adds memory to the picture. A flip-flop remembers

its previous value and only updates on the clock edge. This is what makes

counters count, state machines advance, and our lane FSM track where it

is in the depth-3 intersection pipeline.

The golden rule: Think in registers. Every signal that matters is the

output of a register. Every computation is the combinational path

between two registers. If you remember one thing from this page, let

it be that: register-to-register is the heartbeat of every FPGA design.

This mental model will guide you through timing closure,

pipelining, and all the hardware topics ahead.

Learn more in the deep version

Related: Timing Closure | Pipelines

Soli Deo Gloria