Timing Closure — Brief ☧
Deep version → | Next: Memory → | Back: Registers & Clocks →
Q: The priests of the Temple must complete the morning sacrifice
before the sun rises. If the ritual takes too long, the whole day's
service is disrupted. What is the FPGA equivalent?
A: Timing closure. Remember how we said all combinational logic
must complete between clock ticks? (See Registers & Clocks.)
Timing closure is the process of verifying that this is actually true
for every single path in your design. If even one path is too slow,
data arrives after the clock edge, the flip-flop captures garbage, and
the design malfunctions. It is like a student finishing their exam
answer after time is called — it does not count.
Q: That makes sense, but how do we measure whether we made it?
A: With a number called slack. Think of it like this: if you
have a 60-minute exam and you finish in 55 minutes, your slack is +5
minutes — you had time to spare. If you needed 65 minutes, your slack
is -5 — you ran over. In FPGA terms:
Slack = (clock period) - (combinational delay) - (setup time)The tool reports WNS (Worst Negative Slack) — the slack of the
single slowest path in the whole design. Positive WNS means every path
fits; negative WNS means at least one path is too slow.
Q: Can you give a real example? How close are our designs?
A: Our Rev85b 8-lane build had WNS = +0.043 ns. That means the
slowest path had just 43 picoseconds of margin — less than the
distance light travels across a grain of sand. It works, but barely.
Our 16-lane build had WNS = -0.589 ns, meaning some paths are nearly
0.6 ns too slow. That design fails timing and may produce incorrect
results.
The Three Numbers
After every build, Vivado reports three critical numbers. Learning to read
them is like learning to read a patient's vital signs -- they tell you
immediately whether your design is healthy or in trouble.
| Metric | Meaning | Our 8-lane | Our 16-lane |
|---|---|---|---|
| WNS | Worst path margin | +0.043 ns | -0.589 ns |
| TNS | Total negative slack (sum of all failing paths) | 0 ns | Large negative |
| WHS | Worst hold slack (data stable long enough?) | Should be > 0 | Should be > 0 |
WNS is the single most important number. It tells you the timing margin
of your absolute worst path -- the path that is closest to (or past) the
deadline. If WNS is positive, every path in your design fits within the clock
period and the design is correct. If WNS is negative, at least one path is
too slow and the hardware may produce incorrect results. TNS is the sum
of all negative slacks -- it tells you how many paths are failing and by
how much. A large TNS with a small WNS means many paths are barely failing;
a small TNS with a large WNS means one path is catastrophically slow.
WHS checks the other timing requirement: that data does not change too
soon after the clock edge (the hold time requirement).
Our 8-lane design passed with WNS = +0.043 ns -- barely, with only 43
picoseconds of margin. Our 16-lane design failed with WNS = -0.589 ns,
meaning its slowest paths exceeded the 4 ns clock budget by nearly 15%.
If WNS is negative, you have four options:
- Add pipeline stages to break long paths into shorter ones (see Pipelines)
- Simplify the logic in the critical path
- Improve floorplanning to place related logic closer together (see Resources)
- Reduce the clock frequency (trade speed for correctness)
Soli Deo Gloria