AXI Protocol — Brief ☧
Deep version → | Next: Clock Domain Crossing → | Back: Memory →
Q: Imagine two people on opposite sides of a narrow doorway, one
handing boxes to the other. The sender holds up a box and says "I have
one for you." The receiver opens their arms and says "I am ready."
The handoff only happens when both are true at the same moment.
What is the hardware version of this?
A: The AXI protocol's VALID/READY handshake. In hardware,
the sender raises a signal called VALID ("I have data"), and the
receiver raises READY ("I can accept it"). A transfer happens only
when both signals are high during the same clock tick. This simple
two-signal dance prevents data from being lost or duplicated — no
matter which side is faster.
Q: That covers a single handoff. But a real conversation has
multiple parts — "I want to write here," "here is the data," "got it."
How does AXI handle a full read or write?
A: AXI4 splits communication into five independent channels, like
five separate messengers running between two cities. Each channel uses
its own VALID/READY pair:
Channel Direction Plain English AW (Write Address) Master -> Slave "I want to write here" W (Write Data) Master -> Slave "Here is the data" B (Write Response) Slave -> Master "Got it — write complete" AR (Read Address) Master -> Slave "I want to read from here" R (Read Data) Slave -> Master "Here is what you asked for" Because the channels are independent, a read can happen at the same
time as a write — like having separate incoming and outgoing mail
slots instead of one shared mailbox.
Q: This is like a queue in software, right? One
side pushes, the other side pops?
A: Very similar! In fact, many AXI implementations include small
queues (called FIFOs) inside to buffer data when the
producer is faster than the consumer. The VALID/READY handshake
naturally creates back-pressure: if the receiver's buffer is full, it
drops READY, and the sender waits — just like a bounded
queue that blocks when full.
Q: Why does our design care about all this?
A: Our FPGA talks to HBM through AXI4 (burst transfers for bulk
domain data) and to the host CPU through AXI-Lite (single register
reads and writes via BAR0). Every domain upload, every batch command,
every result readback — all flow through AXI channels. Understanding
the handshake is essential for debugging why data might stall or
arrive corrupted.
The Handshake — Step by Step
Clock: ──┐ ┌─┐ ┌─┐ ┌─┐ ┌─┐ ┌──
└─┘ └─┘ └─┘ └─┘ └─┘
VALID: ___/‾‾‾‾‾‾‾‾‾‾‾‾‾\____
READY: ________/‾‾‾‾\_________
DATA: ---< A >< B >------
^ ^
| |
Transfer Transfer
of A of BA transfer occurs on every rising clock edge where VALID and READY
are both high. No exceptions. This rule is the entire foundation of all
AXI communication.
Soli Deo Gloria